This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to standardized packaging options for integrated circuits.
Some types of integrated circuits are completely custom designed, where each of the electrical devices in the integrated circuit is specifically selected for the custom design, and the integrated circuit is laid out in a customize manner. Such integrated circuits tend to have a relatively large amount of overhead associated with them. For example, there is a large amount of design work involved in producing such a customized integrated circuit. Further, customized mask sets and tooling are required to produce the integrated circuits. When it is expected that a very large number of the integrated circuits will be sold, then it can be cost effective to invest in the overhead associated with the customized integrated circuit, as the overhead can be paid off over a large number of the integrated circuits.
However, there are other applications where such a large number of sales of the integrated circuit is not expected. In these applications, it tends to be cost prohibitive to design the integrated circuit from scratch, so to speak, and to invest in completely customized mask sets and tooling, because there will not be enough of the integrated circuits fabricated to justify such a large investment.
For these smaller-number applications, a different type of integrated circuit is commonly used, called an application specific integrated circuit, or ASIC. ASICs are designed using standardized design elements, or modules, which are combined in a desired configuration to support the intended application. In other words, the design of the integrated circuit is application-specific, as the name implies. ASICs tend to be much cheaper to design and produce than custom integrated circuits, because the standardized design elements have already been designed. Further, mask designs already exist for the design elements. Thus, there is a tremendous head-start on the design process, and ASICs therefore tend to be much less expensive to fabricate than completely customized integrated circuits.
Unfortunately, because the standardized design elements of an ASIC can be combined in a variety of ways, the cost savings associated with standardization have typically not been extended to the packaging used for the ASICs. For example, because different ASICsxe2x80x94even those using similar standardized modulesxe2x80x94tend to be laid out with the standardized modules in different configurations, the package substrate typically requires a different configuration for each such design. Thus, all the costs of a completely customized package design tend to be incurred, even when using standardized modules in an ASIC design.
What is needed, therefore, is a package design with standardized elements for use with an ASIC, which package design can help reduce the costs associated with designing packages for different ASICs.
The above and other needs are met by a package substrate having a first layer adapted to received an integrated circuit, with electrically conductive contacts adapted to send and receive signals to and from the integrated circuit. The first layer includes a ground plane. A second layer is disposed underneath the first layer, and has electrically conductive traces, including a single ended clock signal trace and a set of two differential clock signal traces. The single ended clock signal trace and the set of two differential clock signal traces are substantially surrounded by grounded guard traces from all other electrically conductive traces on the second layer. A first electrically nonconductive layer is disposed between the first layer and the second layer.
In this manner, the package substrate according to the present invention can accommodate either a single ended clock or a differential clock, or both, without the need of specially designing the package substrate for any of the various options. Thus, the design expenses associated with designing packaged integrated circuits using the package substrate are commensurately reduced. If, for example, either the single ended clock or the differential clock is not included in the integrated circuit design, then the structure associated with the unused clock can be used for any other signal routing that may be desired.
In various preferred embodiments, through-holes are disposed in the first electrically nonconductive layer, with electrically conductive vias disposed in the through-holes. The electrically conductive vias preferably make electrical connections between the ground plane on the first layer and the grounded guard traces on the second layer. Preferably, the electrically conductive vias are regularly spaced along the grounded guard traces, and most preferably are regularly spaced along the grounded guard traces at a distance determined at least in part on an operating frequency.
In a preferred embodiment, the package substrate includes a third layer disposed underneath the second layer, where the third layer includes a ground plane. A second electrically nonconductive layer is disposed between the second layer and the third layer. Through-holes are preferably disposed in the second electrically nonconductive layer, with electrically conductive vias disposed in the through-holes. Preferably, the electrically conductive vias make electrical connections between the ground plane on the third layer and the grounded guard traces on the second layer. Preferably, the electrically conductive vias are regularly spaced along the grounded guard traces, and most preferably are regularly spaced along the grounded guard traces at a distance determined at least in part on an operating frequency.
In one embodiment, the third layer is a power plane layer. Most preferably the guard traces surround as much of the single ended clock signal trace and the set of two differential clock signal traces as possible. The guard traces preferably additionally extend substantially between the single ended clock signal trace and the set of two differential clock signal traces.
According to another aspect of the invention there is described a packaged integrated circuit including a package substrate having a first layer adapted to received an integrated circuit. The first layer has electrically conductive contacts adapted to send and receive signals to and from the integrated circuit. The first layer includes a ground plane. A second layer is disposed underneath the first layer. The second layer has electrically conductive traces, including a single ended clock signal trace and a set of two differential clock signal traces. The single ended clock signal trace and the set of two differential clock signal traces are substantially surrounded by grounded guard traces from all other electrically conductive traces on the second layer. A first electrically nonconductive layer is disposed between the first layer and the second layer.